The present disclosure relates to laminated integrated circuit structures, and more specifically to laminated structures that use conductive vias.
Within integrated circuit devices, stresses on laminated structures caused during module assembly or by large thermal gradients, can result in deformation, deflection, or warping of laminate. The effects of the laminate warping are found, for example, during chip assembly processes as it causes open connections between the chip and the laminate. The laminate warping also contributes to module co-planarity. This causes yield loss during card assembly. There are various ways to control the laminate warping, such as appropriate laminate materials selection, selecting appropriate laminate fabrication processes, employing mechanical fixtures during assembly, etc. In some situations, above various ways may not be enough to control laminate warping, and could potentially increase production costs.